STANFORD HPNG TECHNICAL REPORT TR01-HPNG-081501 Techniques for Fast Shared Memory Switches

Shared memory is commonly used to build output queued (OQ) switches. An OQ switch is known to maximize throughput, minimize delay and can offer QoS guarantees. However it is generally believed that high capacity switches cannot be built from shared memory switches because the requirements on the memory size, memory bandwidth and memory access time increase linearly with the line rate and the number of ports . In this paper, we ask the following question: Is it possible to build a highspeed shared memory switch in which the individual memories (in this case, DRAMs) operate at slower than the line rate? We show that this is indeed possible i.e. a shared memory switch with a specific “conflict free DRAM memory management algorithm” (CFDMMA) can emulate a first-come-first-served OQ switch if each memory operates at a rate of approximately , where is the number of DRAMs used in parallel. We also show that the switch can support qualities of service, if the memories operate at a rate of . To enable this, we introduce a small fixed sized co-ordination buffer of size and prove that the shared memory switch can emulate a OQ switch supporting QoS within a relative delay bound of time slots. Keywords--packet-switch; shared memory, packet buffers, outputqueueing;